Verifiable Semiconductor Manufacturing
Issued by
Oxford Martin Artificial Intelligence Governance Initiative
- September 30, 2026 · Correction — Recast the entry as a research paper on chip integrity verification, with its actual title and argument, and removed invented requirements and a 60-day deadline (fact-check finding). (Cody Maxwell)
- October 1, 2026 · Correction — Rewrote the practical steps, newsletter hook, search description, and audience fields to match the entry's corrected content. (Cody Maxwell)
An April 2026 research paper from Oxford's AI Governance Initiative on verifying the integrity of AI chips from design through manufacturing. It argues for defense in depth, tiered by chip criticality, with neutral third-party verifiers. It sets no requirements for anyone.
Applies To
Overview
Aytunc Ilhan, Caleb Withers, Harrison Gietz, and Ben Harack of the Oxford Martin AI Governance Initiative published this research paper on 14 April 2026. It looks at how to assure the integrity of semiconductors used for AI, from design through manufacturing. The paper builds a threat model covering that whole chain and finds no single countermeasure is enough. It argues for a defense-in-depth architecture, with assurance tiered by how critical a chip is. Neutral third-party verification authorities and privacy-preserving data sharing could help overcome industry opacity. It is aimed at policymakers, industry, and international governance bodies. It is a research paper, not guidance, and it sets no requirements or deadlines.
Key Requirements
- •A research paper that sets no requirements for anyone.
- •Builds a threat model for chip integrity from design through manufacturing.
- •Finds that no single countermeasure is sufficient.
- •Proposes defense in depth, with assurance tiered by chip criticality.
- •Suggests neutral third-party verifiers and privacy-preserving data sharing to overcome industry opacity.
What Your Organization Must Do
- →Read the paper as background on AI chip supply chain risk, not as a compliance obligation.
- →Share the threat model with procurement and security teams reviewing hardware suppliers.
- →Map which of your AI chips are most critical, mirroring the paper's tiered approach.
- →Ask hardware vendors what integrity checks they run from design through manufacturing.
- →Watch whether policymakers or international bodies turn these ideas into binding rules.
- →Avoid telling stakeholders the paper creates deadlines or required procedures, because it does not.
Playbook Guidance
Step-by-step implementation guidance for compliance teams.
Frequently Asked Questions
- Is the Verifiable Semiconductor Manufacturing paper legally binding?
- No, it is a research paper from the Oxford Martin AI Governance Initiative, not a regulatory instrument, and it imposes no obligations.
- Who is the paper written for?
- Policymakers, industry, and international bodies working on AI hardware security and cooperation on chip integrity standards.
- Does the paper address AI chip export controls?
- It focuses on hardware integrity rather than export control compliance. It sets no rules for checking components against export classifications.
- What verification mechanisms does the paper propose?
- A defense-in-depth set of measures across design and manufacturing, tiered by chip criticality. It also suggests neutral third-party verification authorities and privacy-preserving data sharing.
- Does the paper apply to all semiconductors?
- It tiers assurance by chip criticality, so the most critical chips get the strongest checks. It does not define a fixed regulatory scope.
- How should compliance teams use the paper?
- Treat it as background for hardware supply chain risk. It sets no deadlines or required procedures.